The present invention is directed to microprocessor control systems, and in particular to systems which employ interrupt requests to control the manner in which a microprocessor executes various system functions.
In microprocessor controlled systems which require a variety of system functions to be controlled in a nonsequential fashion, it is a common practice to employ interrupts to determine the order in which various operations are to be performed by the microprocessor. Each interrupt is generated in response to the occurrence of a predetermined event in the operation of the system. When the microprocessor receives an interrupt request, it halts its ongoing operation at an appropriate point, and proceeds to a predetermined subroutine that controls the function associated with the interrupt that was generated.
Any particular microprocessor architecture arrangement will have a predetermined number of interrupt request lines that are available for use in servicing system functions. For example, a typical VME bus structure might provide six available interrupt request lines. A difficulty arises if the number of system functions to be executed, or the number of interrupt generating events, is greater than the number of available request lines. This type of situation places a burden on the system designer. In particular, it may be necessary to restructure the total system architecture, which could prove to be a costly undertaking. If this is not possible or desirable, then compromises will have to be made in the overall performance of the system, and could result in overburdening the system processor.
Accordingly, it is an object of the present invention to expand the interrupt capabilities of a microprocessor system without restructuring the system architecture.